The AMD 2nd Generation EPYC Rome processors launched in August & since then, we have been getting more details about the chip itself along with its features. The latest details for the I/O die which include close-up die shots have been revealed by Hardwareluxx, giving us a better look at AMD’s most innovative server chip to date.
AMD 2nd Gen EPYC Rome Processor IOD Detailed – 8.34 Billion Transistors on a Single Die, 39.54 Billion on The Entire Chip
There have been many details that AMD has just recently started revealing for their 2nd Gen EPYC Rome processors. The AMD EPYC Rome processors are composed of a 9 die design which is also to be referred to as MCM (Multi-Chip-Module). The 9 dies include eight CCD’s (Compute Core dies) & a single IOD (Input / Output die). Each CCD is composed of two CCX (Compute Core complexes) that feature four Zen 2 cores with their own respective L2 cache and a shared L3 cache. All eight CCD’s are connected to the I/O die using infinity fabric.
Each CCD measures 74mm2 and is composed of 3.9 Billion transistors. The IOD featured on Ryzen has a die size of 125mm2 and is composed of 2.09 Billion transistors. The IOD featured on EPYC is composed of 8.34 Billion transistors and measures at 416mm2. It’s the biggest die on the 2nd Gen EPYC chip. The IOD combined with the 8 Zen 2 CCD’s measure at 1008mm2 while being composed of a whooping 39.54 Billion transistors.
Now the IOD featured on the one is much bigger than the one featured on the Ryzen processors. This is due to the more demanding feature set of the server platforms. When exposed through the use of transillumination, the IO die is clearly exposed and the internal blocks can be revealed much clearly.
It is stated that much of the central space on the IOD is dedicated to the SRAM and crossbar switch while the PCIe Gen 4 interfaces can be found on the sides of the IOD. The upper and lower areas of the die feature the four 72-bit DDR4 memory channels. Now here’s the interesting part, EPYC 2nd Gen has the ability to scale up to 162 PCIe lanes by offering twice the bandwidth through PCIe Gen 4 and reducing the Infinity Fabric’s reliance on the bus to expose more lanes on custom processors that are planned for launch later. The extra PCIe lanes are already there but they are being used by the interconnect.
In addition to the IOD, the Zen 2 CCD or Compute Core Die have also received their own die shots from OC_Burner at Flickr. For those who haven’t seen them before, the following is what each core die of your Ryzen processor looks like. The same die is being used across Zen 2 based Ryzen, EPYC and the upcoming Ryzen Threadripper processors:
Also, the IOD for EPYC processor is compared to the IOD on Ryzen processors revealing just how big of a chip the server-aimed IOD is. AMD already briefed on how they will be configuring various 2nd Gen EPYC Rome processors based on different core counts. While all EPYC Rome chips have a total of 8 CCD’s, not all of them would be enabled on many processors.
Even some CCD’s have to be partially disabled such as the 16 core model. The 16 core model has only four CCD’s enabled & each CCD is partially enabled with only four cores which means there are only 2 cores enabled on each CCX. Some CCD’s have three cores enabled per CCX while others such as the 48 core variant have all 8 CCD’s enabled but two of the CCD’s have a CCX with all four cores enabled and the other with a just three cores enabled.
But this is just the start, AMD is expected to use more advanced packaging and chiplet designs in their next-generation server processors codenamed EPYC Milan and EPYC Genoa which would use the Zen 3 and Zen 4 core architecture, respectively. If everything runs smoothly for AMD and their long-term Zen roadmap in the years to come, we can see them dominating all sectors of the CPU market again. AMD’s EPYC Rome has already secured major deals with Amazon (AWS) and will also be providing 7nm Rome processors to power the Atos BullSequana XH2000 Supercomputer while a future-generation EPYC line would be powering the Frontier Supercomputer that is being built by U.S. Department of Energy and aiming deployment in 2021.